Vehicles, such as aircraft, typically utilise one or more power distribution units to distribute power from a primary power source to various vehicle systems. The solid state power controls in a power distribution unit typically include an electronic switch, such as a FET, and electronic circuitry that provides wiring protection. The FET and circuitry are often referred to as a solid state power controller (“SSPC”). The SSPC has found widespread use because of its desirable status capability, reliability, and packaging density. The Solid State Power Controller (SSPC) is gaining acceptance as a modern alternative to the combination of conventional electromechanical relays and circuit breakers for commercial aircraft power distribution due to its high reliability, “soft” switching characteristics, fast response time, and ability to facilitate advanced load management and other aircraft functions.
While SSPCs with current rating under 15 A have been widely utilised in aircraft secondary distribution systems, power dissipation, voltage drop, and leakage current associated with solid state power switching devices pose challenges for using SSPCs in high voltage applications of aircraft primary distribution systems with higher current ratings.
A typical SSPC generally comprises a solid state switching device (SSSD), which performs the primary power on/off switching, and a processing engine, which is responsible for SSSD on/off control and a feeder wire protection. A typical power distribution unit may include hundreds or thousands of SSPCs.
Solid State Power Controllers are used to switch and regulate current on ohmic, capacitive and inductive loads.
They are also used to absorb inductive energy when switching an inductive load “OFF”. This is done by limiting the voltage over the SSPC (“clamping”) to a specific constant voltage level (clamping voltage) while discharging the load inductance, using the SSPCs linear mode.
In existing SSPC circuits all parallel FETs are directly connected together with their drains and sources. Existing aircraft applications employ exclusively a metal oxide semiconductor field effect transistor (MOSFET) as a basic solid state component for building up the SSSD. This features easy control, bi-directional conduction characteristics, has a resistive conduction nature, and has a positive temperature coefficient. To increase the current carrying capability and reduce the voltage drop or power dissipation, the standard SSSD comprises multiple MOSFETs generally connected in parallel. An example is shown in FIG. 1 using parallel-connected MOSFETs.
When switching an inductive load “OFF”, all paralleled FETs operate in linear mode for a short time (depending on the load, inductive energy, clamping voltage) to absorb the energy from the inductance of the load that has been switched off. The switches are protected by a so-called clamping mode, which involves setting the voltage over the SSPC at a specific maximum voltage level, and using linear mode to absorb the energy that is stored in the inductance.
As not all FETs have the same gate threshold voltage Vth because of process and production variations, current is shared very unequally between FETs in this conventional linear mode.
The problem in such applications is to really control the current or energy sharing over the paralleled solid state devices equally. This problem occurs during linear mode operation during switch off of an inductive load. Generally, during SSSD turn-off transients, all of the MOSFETsn do not turn off simultaneously, nor does the current distribute evenly among the MOSFETs in such a short time.
This is specifically true for FETs that have a very steep transfer characteristic like many Si MOSFETs that are optimised for pure switching On/Off applications.
This imbalance in linear mode gets worse after a few μs because the hottest FET will take even more current, because the gate threshold voltage Vth of a FET drops with increasing temperature. Because all FETs see the same Vgs voltage from the gate driver, a single FET with lower Vth will take much more current.
This leads to a mechanism in linear mode where the FET that is already the hottest will take the largest amount of current, thus leading to uneven current distribution.
There is no mechanism in linear mode that works against such an imbalance.
The result is that some FETs in a paralleled FET array get much hotter than the rest. Energy sharing variation amongst the FETs can be 100% and more. Therefore, the likelihood of destroying a single FET in a paralleled array is very high, even if the operated pulsed energy average is in the middle of the SOA area (theoretical average energy per FET of a FET array).
This fact raises the costs in SSPC design because it is necessary to design a very high safety margin into the SSPC to make sure that the FET with the lowest Vth is not destroyed. A destroyed FET in an SSPC causes in most cases a short circuit between its G-D-S connections, which makes the whole SSPC unusable. If the FET is mounted in “Chip On Board” technology, it is also not repairable.
Because of the goal for an SSPC to achieve the lowest possible voltage drop, it is not an option to add additional resistors at the MOSFET sources in the way it would be implemented in a conventional current feedback design for discrete FETs of current amplifiers for example.
In an SSPC capable of operating in AC conditions, because of the FETs inherent body diode, FETs are needed that are directed towards both current directions, to be able to interrupt AC current.
It is desirable to have an SSPC design in which the current can be more controlled and more evenly distributed between FETs when an inductive load is switched off.